This invention relates to microelectronic memories and, more particularly, to floating gate memory devices.
In recent years considerable effort has been devoted to the development of GaAs-based static random access memories (SRAMS). There has been, on the other hand, very limited activity on dynamic random access memories (DRAMS), although AlGaAs/GaAs structures for such applications have been proposed. See, for example, T. E. Dungan et al., IEEE Electron Dev. Lett., Vol. EDL-8, p. 243 (1987), M. R. Melloch et al., Appl. Phys. Lett., Vol. 49, p. 1471 (1986), and M. R. Melloch et al., Appl. Phys. Lett., Vol. 50, p. 1657 (1987). Likewise there has been little, if any, work on GaAs-based read only memories (ROMs) whether electronically programmable (EPROMs) or not.
Previously, however, workers in the art have demonstrated the storage of carriers in heterostructures following hot electron injection by real-space transfer (M. Keever et al., IEEE Electron Dev. Lett., Vol. 3, p. 297-299 (1982)). Luryi et al. observed a long-term memory effect in a charge injection transistor at 77.degree. K. when the collector electrode was disconnected (S. Luryi et al., Appl. Phys. Lett., Vol. 45, p. 1294-1296 (1984)). This effect is due to charge accumulation in the floating substrate due to hot electron injection. Hot electron programmable random access memories based on the effect were subsequently proposed (S. Luryi et al., Superlattices and Microstructures, Vol. 1, p. 389-400 (1985)).
An important class of Si-based non-volatile memories utilize floating gate devices which are described by S. M. Sze, Physics of Semiconductor Devices, Wiley, New York (1981), p. 496. These devices are currently being commercially used in a large variety of applications ranging from computers to microprocessor-controlled equipment. In conventional Si-based floating gate memory devices, electrons are injected from the channel into a polysilicon floating gate surrounded by insulators. Injection occurs via either an avalanche or a tunneling mechanism after application of a large positive voltage (several tens of volts) to the control gate. The stored charge in the floating gate then modifies the channel conductance. To erase the memory a large negative voltage is applied to the control gate so that the charge is injected from the floating gate back into the channel by tunneling.
The standard Si-based floating gate memory circuit utilizes the same electrical path to perform the read and write functions and a single FET to control current flow in that path. Three voltage levels, including a switched power supply, are used to perform read, write and erase functions (Ong, D. G., Modern MOS Technology: Processes, Devices & Design, McGraw Hill, 1984, pp. 215-217.